2023 VLSI Design / CAD Symposium 第34屆超大型電路設計暨計算機輔助設計技術研討會

從Yolov4 到 Yolov7的發展過程

廖弘源

中央研究院資訊科學研究所／特聘研究員兼所長

8月2日(三)｜09:30-10:30・6F 義大演講廳

Bio

廖弘源1981年由國立清華大學取得物理學士，並於1990年取得美國西北大學電機博士。1991年7月應聘回中央研究院資訊所，2012年升為特聘研究員。他於1997年至2000年間擔任資訊所副所長，並於2018年8月受聘為資訊所所長。

廖博士致力於多媒體訊號處理、影像處理、以視訊為主的人類行為分析、三維圖形的分割及辨識等研究領域超過25年。曾任IEEE Signal Processing Magazine、 IEEE Transactions on Image Processing (2009-2013)、IEEE Transactions on Information Forensics and Security (2009-2012)等期刊的編輯，目前亦擔任ACM Computing Survey的副編輯。

廖博士曾獲得許多獎項，包括中央研究院年輕學者著作獎（1998，國科會傑出研究獎(2003、2010及2013)，以及中央研究院深耕計畫獎(2010)。他也獲得中華民國資訊學會博士論文指導獎。 2016年他獲得東元科技獎；他因在image and video forensics and security的貢獻，於2013 年獲選為 IEEE Fellow。廖博士另於2020年獲得教育部第六十四屆學術獎，並於2023年獲國科會傑出特約研究員獎

Abstract

YOLOv4及YOLOv7的發展過程是有一段故事的。2018年初我的實驗室拿到一個四年期的科技部AI專案計畫。科技部希望我們與業界合作。我們挑了智慧交通解決方案來執行。因為所有的運算需在edge端完成，間接造就了YoLov4及YoLov7的發展，也意外的讓一系列的物件偵測系統在世界上發光發亮。

From Atoms to Systems, EDA AI/ML Innovation in the SysMoore Era

李明哲

新思科技股份有限公司／台灣新思科技董事長暨總經理、新思科技全球銷售副總裁

8月2日(三)｜11:00~12:00・6F 義大演講廳

Bio

Dr. Robert Li is currently the Sales VP and Chairman of Synopsys Taiwan. Before this role, he was leading a global team to support the major foundry and its eco-system in advanced process development, technology partnership, and mutual customer collaboration. Dr. Li was with Synopsys Professional Service group in 1999, rejoined Synopsys/Taiwan sales team in 2003, and lead a team covering key accounts and Greater China foundry business till moving to Synopsys, China. As the Country Manager with Synopsys China, he built and lead a strong field team with creditable business outcome and satisfactory customer relationships since Dec. 2009. With his 20+ years of working experience in the wireless and semiconductor industry, Dr. Li’s role covers technology research, production/project planning/management, sales marking, and business operation._1/2normalized by l/NA, i.e. P_1/2/(l/NA) = k₁, is an indicator of the performance of the imaging system. The smaller the better. When k₁³ 0.6, the designer has a lot of freedom in the shapes and placement of the features of his design. In ultimate lithography, k₁ can be as small as 0.08 which has progressed by a factor of 1/Ö2 over 6 generations from k₁=0.6. The design would be progressively restricted. This presentation shows how k₁ progresses through these stages and the resulting restrictions imposed to the designers. These restrictions cannot be avoided. Otherwise, an i-line system with NA=0.6, k₁=0.6 implies a half pitch of 365 nm instead of 48.7 nm for k₁=0.08. A 193-nm water-immersion system with l=134 nm can resolve only 84.6-nm half pitch, worse than the i-line system with ultimate resolution. However, when k₁=0.08 is achieved on the immersion system, 11.3-nm half pitch can be realized.

Abstract

In the SysMoore era, we are facing a lot of challenges. This talk will cover “The Five Overarching Themes” in the current IC design, including (i) PPA push, (ii) First Tapeout works, (iii) Multi-die/3D systems, (iv) Safe, secure, resilience silicon, and (v) Productivity. How Synopsys EDA uses AI/ML to cope with those challenges.

AI晶片的技術發展與應用趨勢

張世杰

工業技術研究院電子與光電系統研究所／所長

8月3日(四)｜09:00~10:00・6F 義大演講廳

Bio

現任	工研院電光系統所所長、國立清華大學資訊工程學系教授
學歷	學士/ 國立台灣大學電機工程學系碩士/ University of California, Santa Barbara, Electrical and computer engineering 博士/ University of California, Santa Barbara, Electrical and computer engineering
經歷	Synopsys, USA，資深工程師(1994 ~ 1996) 國立中正大學資訊工程系, 副教授 (1996.08 ~ 2001.07) 國立清華大學資訊工程系, 副教授 (2001.08 ~ 2002.07) 國立清華大學資訊工程系, 教授 (2002.08 ~ 迄今) 工研院電光系統所副所長/技術長(2018.08 ~ 2022.03)
榮譽	2013 中國電機工程師學會102年度「傑出電機工程教授獎」 2016 科技部104年度傑出研究獎

Abstract

人工智慧改變了我們生活的各方面，而AI晶片是這場革命的核心。AI加速器是能夠針對AI運算大量的輸入資訊，提供高效能、低功耗的計算能力。本演講將介紹AI加速器的種類、軟硬體整合和應用範例，例如自駕車和語音辨識。此外，亦將討論後摩爾時代最關鍵的異質整合技術，透過先進封裝把具有不同功能和特性的晶片結合起來，克服單一晶片的限制和挑戰。小晶片(chiplet)則是在高效能運算需求下，提升製造良率、降低成本和加速開發的關鍵技術，而chiplet的介面標準更是至關重要。透過這些具有挑戰和潛力的技術，我們將能更深入地了解AI晶片技術和創新應用的未來新趨勢。

Advanced Packaging Design for Heterogeneous Integration

洪志斌

ASE Group／副總經理

8月3日(四)｜10:20~11:20・6F 義大演講廳

Bio

Dr. C.P. Hung currently holds the position of Vice President, Corporate R&D, at ASE Group. Based in Taiwan, he leads teams responsible for next-generation product development featuring integrated technologies, as well as a broad range of advanced chip, package, and system integration solutions with multiple ASE and USI Sites. During his tenure, Dr. Hung has performed a variety of management roles at ASE, including VP of Corporate Design, VP of Central Engineering & Business Development and VP of Logistic Services Integration. He holds 180 patents encompassing IC packaging structure, process, substrate and characterization technology. He has also published over 105 conference and journal papers. Dr. Hung has being the SEMICON Taiwan PKG & TEST Committee Chair since 2013, and currently Co-Chair since 2021. He is also a board of governor of IEEE EPS since 2019.

Abstract

Advanced IC Packages are typically Ball Grid Array (BGA) and Flip-Chip (FC) based with various structures to meet demanding high performance computing needs. This presentation will discuss innovative BGA and Fan-Out with FC technologies - FOCoS and 2.5D / 3D packages, describing how the design needs are optimized with higher precision, effective layout with enhanced electrical signal and power performance, very essential for new generation AI server, data center, 5G and latest edge computing applications.

環境永續與未來產業

吳誠文

南臺科技大學／校長

8月4日(五)｜09:00~10:00・6F 義大演講廳

Bio

學歷：1981台大電機系學士；1985 UCSB MS-ECE；1987 UCSB PhD-ECE

經歷：成功大學副校長、成功大學敏求智慧運算學院講座教授、工研院資深副總兼首席技術專家、行政院科技會報首席評議專家室主任、清華大學積體電路設計技術研發中心主任（創立）、清華大學副校長、工研院資訊與通訊研究所所長、工研院系統晶片科技中心主任、清華大學電機資訊學院院長、清華大學電機工程學系主任、清華大學計算機中心主任、清華大學電機系特聘講座教授

專長：半導體記憶體測試與修復；晶片系統設計與測試

榮譽：2004 IEEE Fellow；2005教育部學術獎；2010東元獎；2013教育部國家講座；2015中國電機工程學會電機工程獎章；2018科技部傑出特約研究員獎；2020潘文淵文教基金會研究傑出獎

Abstract

因為人類過度消耗地球資源造成環境惡化及地球暖化，衍生出一項議題就是淨零碳排的目標，它促成了運具電動化以及智慧綠能的發展，未來會改變很多的行業。未來科技從業人員一輩子只從事一件工作的時代可能已經過去，我們必須要面對跨領域的問題與挑戰，要無時無刻與時俱進的吸收新知，才能在一波波的新世代挑戰中站穩腳步，大步向前。我會試著從不同角度探討TICD會員可能會關心的未來社會與產業的發展。

Keynotes